Cadence Design Systems, Inc. today announced the immediate availability of an integrated system design solution for TSMC’s advanced wafer-level Integrated Fan-Out (InFO) packaging technology, resulting from a collaboration between Cadence and TSMC that was announced earlier this year. Cadence is now offering implementation, signoff and electro-thermal analysis tools that enable concurrent multi-chip optimization for designs that incorporate InFO.
The Cadence solution includes:
- Cadence System-in-Package (SiP): Provides the InFO design and layout platform with enhanced features to generate the complete layout of the system, in-design design rule checking (DRC), and IC-level physical signoff.
- Multiple extraction solutions at the chip and package level: The Quantus™ QRC Extraction Solution and Allegro®-Sigrity™ Package Assessment and Extraction Option are specifically tailored for verifying InFO applications.
- Multiple IC signoff solutions: The Tempus™ Timing Signoff Solution provides cross-die/cross-InFO timing checks, the Voltus™-Sigrity Package Analysis offers multi-die concurrent electro-migration IR drop (EMIR) analysis, and the Cadence Physical Verification System (PVS) provides DRC and layout versus schematic (LVS) checking for InFO systems and heterogeneous dice.
- Sigrity IC package analysis and 3D modeling: Enables layer-based thermal, electro-magnetic interference (EMI), static and dynamic IR analysis, and a thermal-aware EM multi-die InFO system.
“The new flow provides customers with an unparalleled, holistic IC and packaging solution that covers the full spectrum of heterogeneous, multi-chip designs in InFO technology,” said Tom Beckley, senior vice president and general manager, Custom IC & PCB Group at Cadence. “By working closely with TSMC, we are enabling our mutual mobile and IoT customers to further shorten system design and verification cycle times so they can get to market faster.”
“We’ve seen continued demand for our InFO packaging technology because designers have the ability to integrate multiple chips into a single package while increasing design performance,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Through our ongoing collaboration with Cadence, we’re bringing expanded capabilities to our customers so they can boost productivity and overcome competitive market pressures.”
