Synopsys, Inc. announced that in collaboration with Samsung Foundry, more than 30 new interoperable process design kits (iPDKs) have been jointly developed, validated and support the Synopsys Custom Design Platform. These iPDKs provide broad coverage for Samsung Foundry's portfolio of advanced and legacy nodes. The Synopsys Custom Design Platform is a faster and more productive design and verification solution that delivers up to 5X faster layout and 2X faster design closure, providing maximum productivity to users of a wide range of Samsung Foundry process technologies.
The Synopsys and Samsung collaborative effort included developing and validating a complete set of Samsung iPDKs, methodologies and design flows. Synopsys and Samsung also collaborated on implementing a comprehensive iPDK development and validation solution, based on Synopsys Custom Design Platform, that leverages the Custom Compiler™ design and layout environment. This environment includes HSPICE® circuit simulator, FineSim® circuit simulator, CustomSim™ FastSPICE circuit simulator, Custom WaveView™ waveform display, StarRC™ signoff extraction, and IC Validator physical verification.
"We are committed to addressing our customers' needs of deep expertise in technologies and complex custom designs. Samsung Foundry sees a growing request for Synopsys' Custom Design Platform and its design and verification solutions," said Jongwook Kye, vice president of Design Enablement Team at Samsung Foundry. "In close collaboration with Synopsys, the industry leader providing comprehensive custom design and innovative EDA solutions, we have set a new bar of optimized flows and iPDKs based on our process technologies. Samsung Foundry certified Synopsys' differentiated design and verification flows and solutions that will help designer efficiency at our various nodes."
The broad library of over 30-plus Samsung and Synopsys iPDKs range from advanced gate-all-around or FinFET nodes including 3nm to 14nm, and many legacy nodes from 65nm to 130nm, enabling designers to access advanced features. The iPDKs enable designers to leverage analog and mixed-signal integrated circuits and IP using the latest Synopsys suite of custom implementation solutions. Each iPDK includes documentation and design infrastructure elements such as: simulation models for various devices, layer map and technology files, design rule check and layout versus schematic runset files for physical and electrical design rules verification, parasitic extraction deck, schematic symbol library, and parameterized cells, as well as power and performance optimizations used to help customers make the best chips.
"Today's IP and analog design community face increasing challenges from complex layout rules, stringent analog closure requirements and aggressive design schedules. Instead of depending on a set of point tools, they need a robust custom design platform that integrates signoff technologies and simulation workflows to deliver higher productivity," said Aveek Sarkar, vice president of Engineering, at Synopsys. "With our deep collaboration with industry leaders, such as Samsung, we're driving key innovations for our methodologies, reference flows and iPDKs. We look forward to our continued opportunities for excellence with Samsung to fuel further technology innovation for high-growth markets and our growing customer ecosystem."
Learn more details about the best-practices for efficient design and verification, leveraging broad and robust iPDK support, design flow methodologies and enablement optimized for Samsung Foundry process technologies, as Ravi Rao, group director of Applications Engineering at Synopsys, will be presenting on October 28 at the upcoming Samsung Advanced Foundry Ecosystem (SAFE) Forum. For more information regarding Synopsys products, visit: https://www.synopsys.com/implementation-and-signoff.html.
