Cadence announced the industry’s first LPDDR5X 9600Mbps memory IP system solution designed specifically for enterprise and data center applications with high reliability. This innovative solution integrates Cadence’s production-proven LPDDR5X IP and Microsoft’s advanced redundant array of independent double data rate (RAIDDR) error correction code (ECC) coding schema, delivering a powerful combination of high performance, low power consumption and robust reliability. Microsoft is the first customer to deploy the new system solution.
In the AI infrastructure build-out, LPDDR5X is gaining traction in the data center due to its ability to boost energy efficiency and performance for AI, HPC and other memory-intensive workloads. While LPDDR5X-based systems reduce power consumption and run times, hyperscalers have until now faced a tradeoff between power, performance and area (PPA) and the reliability, availability and serviceability (RAS) offered by DDR5 memory.
Built on LPDDR5X DRAM technology, the new memory IP system solution enables enterprise RAS capabilities while maintaining PPA in a compact form factor. The solution supports up to 9600Mbps data rates and offers sideband ECC performance comparable to traditional DDR5 ECC implementations, making it ideal for data center applications.
At the core of the solution is Microsoft’s RAIDDR ECC coding schema—a next-generation error correction algorithm that achieves close to single device data correction (SDDC), providing industry-leading accuracy and fault detection with minimal logic overhead. RAIDDR offers protection equivalent to symbol-based ECC, traditionally associated with DDR5 RDIMM-based applications.
Key features of the new memory system solution include:
- Support for 40-bit channels using LPDDR5X DRAM
- 9600Mbps performance combined with low power consumption
- Enterprise-grade RAS with DDR5-style symbol-based ECC reliability
- Sideband ECC support for maximum channel bandwidth
- Compact form factor for space-constrained systems
“Our LPDDR5X 9600Mbps system solution marks a major milestone in memory innovation for the enterprise and data center markets,” said Boyd Phelps, senior vice president and general manager of the Silicon Solutions Group at Cadence. “By combining the speed and power efficiency of LPDDR5X with the reliability of Microsoft’s innovative RAIDDR ECC technology, we’re delivering a solution that redefines what’s possible in high-performance, low-power memory systems.”
“Microsoft is proud to introduce RAIDDR, our next-generation enterprise DRAM symbol-based ECC algorithm, which delivers high accuracy and reliability,” said Saurabh Dighe, corporate vice president of Systems Planning and Architecture at Microsoft. “By collaborating with Cadence and using their LPDDR5X system IP, we are driving the industry’s adoption of high-performance, lower power data center solutions.”
Available as complete subsystems, Cadence’s memory IP solutions are designed for high-performance AI training and inference applications. In July 2025, Cadence introduced the industry’s first LPDDR6 memory IP system solution operating at speeds of 14.4Gbps—providing customers with a strong roadmap for future performance upgrades. Cadence offers a comprehensive portfolio of silicon-proven, PPA-optimized memory and interface IP for HPC and AI applications, including the latest versions of key industry standards such as LPDDR, HBM, DDR5, PCI Express® (PCIe®), Universal Chiplet Interconnect Express™ (UCIe™), UALink, Ultra Ethernet and high-speed Ethernet with broad solutions that include verification IP and support for chiplets, including 3D-ICs.
