Siemens announced the latest continued collaboration with Samsung Foundry, reinforcing joint efforts to enable advanced semiconductor design and manufacturing workflows for the global fabless ecosystem.
Through close engineering alignment, Siemens continues to qualify and deploy its electronic design automation (EDA) software - including design, verification, simulation and silicon manufacturing enablement - with Samsung Foundry’s latest process technologies. These efforts are focused on improving design quality, accelerating time to market and increasing confidence in first-pass silicon success at Samsung’s advanced nodes.
“Samsung Foundry continues to work closely with Siemens to support customers with robust, manufacturing-ready design flows across advanced process technologies,” said Hyung-Ock Kim, vice president and head of the Foundry Design Technology Team, Samsung Electronics. “Through our collaboration within the SAFE ecosystem, we are aligning proven EDA solutions with our process platforms to help customers address increasing design complexity, improve verification confidence, and accelerate innovation from design through manufacturing.”
“Our continued collaboration with Samsung Foundry reflects Siemens’ commitment to delivering production-ready EDA solutions aligned with the world’s most advanced process technologies,” said Ankur Gupta, executive vice president, IC Portfolio, Siemens EDA Siemens Digital Industries Software. “By working closely with Samsung, we are helping mutual customers to manage design complexity and bring innovative products to market with greater confidence.”
Photonic integrated circuit verification
Siemens and Samsung Foundry are expanding collaboration in photonic integrated circuit (PIC) verification to address the growing complexity of photonic designs. Built on Siemens Calibre® software, the joint solution supports equation-based design rule checking, curvilinear layout versus schematic verification, and advanced pattern matching. These capabilities enable accurate verification of complex curvilinear geometries and manufacturable PIC designs within Samsung Foundry process flows.
Physical verification and layout optimization
For physical verification and layout optimization, Calibre nmPlatform software - including nmDRC, nmLVS, PERC and xACT and Calibre DesignEnhancer - is fully qualified for Samsung Foundry processes. To address escalating power integrity challenges, Samsung Foundry is working closely with Siemens to strengthen power-grid robustness through automation. As part of this collaboration, Samsung Foundry plans the official release of Calibre DesignEnhancer Pge for 2nm, leveraging its ability to automatically enhance the power grid and proactively mitigate electromigration and IR drop issues via intelligent layout optimization. DesignEnhancer Via and Pge automatically implement DRC-clean metal and via layout modifications. This integration supports a shift-left methodology that improves engineering productivity and design reliability at advanced nodes.
Design-for-test and yield analysis
Siemens’ Tessent™ design-for-test portfolio plays a key role in the collaboration by enabling scalable DFT methodologies for advanced-node yield analysis. Joint work focuses on defect-oriented test strategies and physical failure analysis to help reduce defective parts per million. A notable milestone is the establishment of a high-resolution chain diagnosis reference flow at Samsung Foundry using Tessent HiRes Chain Diagnosis, enabling cell-aware, layout-aware and silicon-proven global signal diagnosis for improved failure isolation.
Advanced packaging and 3D IC integration
In advanced packaging, Samsung Foundry has adopted Siemens solutions to support its 2.3D Cube-E advanced package platform. Innovator3D™ IC Integrator enables early-stage full-project floorplanning and rapid response to design changes, while Innovator3D IC Layout automates daisy-chain netlist generation for designs exceeding two million pins. Comprehensive physical verification, including DRC and LVS, is performed using Calibre® 3DStack and Innovator3D IC to ensure design integrity for complex 2.5D and 3D IC implementations.
Analog, RF and library verification
For analog, RF, and library verification, Siemens’ Solido™ Simulation Suite, including Solido SPICE, Analog FastSPICE (AFS) and Solido LibSPICE, is qualified for SPICE-accurate verification across Samsung Foundry process technologies. The collaboration includes first-time qualifications for automotive applications on 4nm and 2nm, as well as support for third-generation 4nm and second-generation 2nm technologies, along with updated model support spanning FD-SOI, FinFET and MBCFET technologies from 18nm through 2nm. Further, Solido SPICE and AFS enable accurate aging and reliability analysis through Open Model Interface (OMI) support for 14nm through 2nm. The collaboration further extended with formalized reference flows on the foundry’s 2nm node with Solido’s simulation, environment, characterization and IP validation technologies, to benefit mutual customers.
Digital implementation
In digital implementation, Aprisa™ software is fully certified for Samsung Foundry leading-edge process nodes. Through ongoing collaboration with Samsung Foundry, Siemens EDA continues to optimize performance, power, and area (PPA), enabling customers to accelerate design closure for their next-generation designs on Samsung Foundry processes.
