For more information on the Palladium Z1 emulation platform, please visit www.cadence.com/go/PalladiumZ1.
Acacia selected the Palladium Z1 platform for the development of its DSP ASICs due to the platform’s ability to execute synthesizable models at speeds far greater than classic simulation, enabling Acacia to execute tests that were not previously possible, while also helping ensure that the ultra-low-power requirements were being met.
“In order to build a high-performance, low-power optical module, we needed a solution that could accommodate designs of up to 650M gates,” said Jon Stahl, director of ASIC at Acacia Communications. “The Cadence Palladium Z1 Enterprise Emulation Platform was the best choice, meeting our complex requirements for our DSP ASIC development. The Palladium Z1 platform proved to be easy to adopt, manage and scale, providing our engineering teams with the ability to deliver high-quality, innovative designs while adhering to tight deadlines. In particular, we found the cloud-based model, the debug features, and the top-notch support, to be compelling reasons to choose this solution.”
The Palladium Z1 Enterprise Emulation Platform is part the Cadence Verification Suite, comprised of best-in-class core engines, verification fabric technologies and solutions that increase verification throughput. The Verification Suite supports the Cadence Intelligent System Design strategy, enabling SoC design excellence.
