Cadence Design Systems, Inc. announced that the new release of the Cadence® digital full flow—proven with hundreds of completed advanced-node tapeouts—has been enhanced to further optimize power, performance and area (PPA) results across a variety of application areas including automotive, mobile, networking, high-performance computing and artificial intelligence (AI). The flow features multiple industry-first capabilities including unified placement and physical optimization engines plus machine learning (ML) capabilities, enabling design excellence with up to 3X faster throughput and up to 20% improved PPA.
“The new digital full flow enhancements build upon the widely adopted integrated flow, further advancing Cadence’s digital and signoff design leadership position and enabling customers to achieve SoC design excellence,” said Dr. Chin-Chi Teng, senior vice president and general manager of the Digital & Signoff Group at Cadence. “We’ve collaborated closely with our customers who are under pressure to meet compressed schedules with increasingly large designs, offering them the features they need to realize PPA gains more efficiently.”
The Cadence digital full flow consists of the Innovus Implementation System, Genus Synthesis Solution, Tempus™ Timing Signoff Solution and Voltus™ IC Power Integrity Solution. It provides customers with a fast path to design closure and better predictability and supports the company’s Intelligent System Design™ strategy, which enables advanced-node system-on-chip (SoC) design excellence.
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