Synopsys, Inc. announced that Achronix Semiconductor Corporation achieved first-pass silicon success for its new Speedster7t FPGA using comprehensive design, verification and IP solutions from Synopsys. Achronix selected Synopsys to meet the high-bandwidth and artificial intelligence/machine learning (AI/ML) workload requirements of its high-performance computing FPGA design while accelerating time-to-market.
"Achronix's new 7-nm Speedster7t FPGA supports the massive amounts of data processing required for high-performance applications," said Chris Pelosi, Achronix VP of Hardware Engineering. "Selecting Synopsys verification and golden-signoff-enabled design technologies helped our team achieve better overall design convergence. Additionally, we accelerated our schedule by months due to the easy integration of the high-quality Synopsys DesignWare IP. The breadth of solutions from Synopsys helped us to both minimize design risks and achieve our stringent design and time-to-market targets."
The Synopsys DesignWare® IP portfolio helped Achronix meet the Speedster7t FPGA's memory performance and real-time data connectivity requirements. Compared to competitive solutions, the DesignWare Logic Library IP offers 4% better area and an 8% improvement in timing, which is significant for high-speed designs. In addition, the DesignWare Embedded Memory IP, including dual-port SRAMs, reduced the Speedster7t FPGA's power consumption. The DesignWare DDR4 IP offers comprehensive and extensive reliability, availability and serviceability (RAS) capabilities. The low-latency DesignWare IP for PCI Express (PCIe) 5.0, with 512-bit datapath width supporting x16 links, provides maximum bandwidth and power efficiency. Achronix plans to continue its longstanding collaboration with Synopsys by using DesignWare IP in its next design.
The Synopsys Fusion Design Platform™ was critical to Achronix achieving the performance necessary to deliver market-shaping levels of high-bandwidth compute in both an area- and power-constrained form factor. The unique fusion of test, implementation and golden-signoff technologies enabled the company to minimize design margins on a broad and systemic scale, achieve better overall design convergence and accelerate its ability to achieve right-first-time silicon.
The Synopsys Custom Design Platform was instrumental in reducing the time and effort required to design, lay out and simulate the high-performance custom circuits in the 7-nm Speedster7t FPGA, with node-specific features that improved designer productivity.
Achronix also adopted key functional verification products from the Synopsys Verification Continuum® Platform to verify its FPGA. Synopsys' VCS® simulation solution enabled accelerated simulation performance, while its Verification IP delivered faster verification environment creation and VC SpyGlass™ RTL static signoff tool provided early detection of design bugs.
"Hyperscale data center designs continue to evolve due to tremendous internet traffic growth, requiring a combination of high-performance and low-latency solutions to help deliver total system throughput," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. "Synopsys provides companies such as Achronix with the industry's most comprehensive design, verification and IP solutions that address the stringent requirements of high-performance computing designs."
Industry-Leading Solutions from Synopsys
Achronix's Speedster7t FPGA features an array of new machine learning processors (MLPs) optimized for high-bandwidth and AI/ML workloads. The company achieved optimal benefit from utilizing multiple Synopsys solutions, including:
- Fusion Design Platform (including Design Compiler®, IC Compiler™ II, PrimeTime®, PrimePower, StarRC™, and SiliconSmart®)
- Custom Design Platform (featuring Custom Compiler™ and PrimeSim™ Continuum)
- IC Validator™
- Verification Continuum Platform (featuring VCS, VC SpyGlass and Verification IP (VIP))
- DesignWareIP
