Cadence Design Systems, Inc. announced Global Unichip Corporation (GUC) used the Cadence® digital full flow to accelerate the time to tapeout of its ASIC designs for mobile, automotive, AI and hyperscale computing applications. By leveraging the Cadence Innovus™ Implementation System’s mixed-placer automation technology, GUC successfully reduced floorplan design time from weeks to days and achieved more than 10% reduced wirelength and 5% better switching power.
GUC has been using the Cadence digital full flow for many years to tape out the most challenging ASIC designs down to the latest 5nm and 3nm process nodes. As a leading global ASIC provider, delivering the best power, performance and area (PPA) results within ever more demanding schedules is critical for success.
As ASIC designs grow in size and complexity, the number of macros in a floorplan also increases rapidly, making GUC’s traditional manual and iterative floorplanning process a lengthy part of the implementation schedule. Using the Innovus mixed-placer technology, the GUC team can handle the placement of both standard cells and macros concurrently, automating the floorplanning process to achieve greater efficiency and faster PPA analysis.
“As our ASIC customer designs move to the latest process nodes and grow in size and complexity, GUC is always making strategic investments in the latest technologies that ensure we can meet and exceed customer requirements for optimal PPA,” said Louis Lin, senior vice president at GUC. “Cadence’s Innovus mixed-placer technology enabled us to make a significant productivity breakthrough, so that we could complete customer designs more efficiently and accelerate tapeout. The Innovus mixed-placer technology is now a key part of our GUC production implementation flow, providing many tapeout successes, and we use it for the majority of our designs.”
The Cadence digital full flow provides customers with a fast path to design closure and better predictability. It supports the company’s Intelligent System Design™ strategy, enabling SoC design excellence.
