Siemens Digital Industries Software has announced that Pearl Semiconductor, a fabless semiconductor company specializing in high-performance timing products, used Siemens‘ Symphony™ Mixed-Signal Platform for developing and verifying its newest ultra-low noise digital phased locked loop (PLL) design, which targets a range of demanding applications such as high-speed connectivity, high bandwidth video broadcasting and 5G infrastructure markets.
Leveraging the fast simulation performance of Siemens‘ Symphony Mixed-Signal Platform, Pearl Semiconductor rapidly achieved silicon-accurate simulation for its latest PLL offering, while boosting functional verification cycles by 4x. This dramatic acceleration helped Pearl achieve aggressive time-to-market objectives.
“With the exponential rise of data due to digitization, the need for a worldwide upgrade of bandwidth and data network infrastructure is happening at a rapid pace,“ said Mohamed Dessouky, vice president of engineering for Pearl Semiconductor. “High-performance timing solutions like our latest PLL offering play a key role in increasing bandwidth for network ICs. Our novel PLL architecture continuously suppresses spurs, while minimizing the noise contribution of active circuitry within the PLL bandwidth. Designing these complex circuits requires a robust mixed-signal verification solution, and this is why we selected Siemens’s Symphony Mixed-Signal Platform for extensive mixed-signal verification of our PLL designs The flexibility of Symphony to work with our mixed-signal use cases and the tool’s ease-of-use resulted in wider adoption across our verification teams and resulted in 4X productivity improvement.”
Powered by Siemens’ Analog FastSPICE (AFS) technology, the Symphony Mixed-Signal Platform combines the leading foundry-certified circuit simulator with industry-standard hardware description language (HDL) simulators to provide fast and accurate verification of complex nanometer-scale mixed-signal integrated circuits (ICs). The platform’s modular architecture leverages Siemens‘ AFS circuit simulator software to provide exceptionally fast mixed-signal simulation performance with nanometer-scale SPICE accuracy and compatibility with all leading digital solvers, including Siemens‘ Questa™ functional verification tool family.
"The need for ultra low-noise high bandwidth timing solutions is becoming critical in many applications, and mixed-signal innovations such as Pearl's DSP+analog-based solutions are critical to meet those requirements," said Ravi Subramanian, senior vice president and general manager for the IC Verification Solutions Division at Siemens Digital Industries Software."We are pleased that our Analog FastSPICE and Symphony Mixed Signal Platforms played a key role in Pearl’s development of their latest ultra-low noise digital PLL design.“
