Cadence Design Systems, Inc. announced that it has demonstrated interoperability between the silicon-proven Cadence® LPDDR5X memory interface IP and SK hynix’s LPDDR5T (Turbo) mobile DRAM, operating at speeds in excess of the LPDDR5X standard. This milestone follows Cadence’s earlier announcement of the first LPDDR5X memory interface IP design operating at 8533Mbps and SK hynix’s first announcement of its LPDDR5T mobile DRAM technology operating at 9600Mbps.
Available now for customer engagements, the Cadence LPDDR5X IP boasts a new high-performance, scalable and adaptable architecture based on Cadence’s proven and highly successful LPDDR5 and GDDR6 product lines. The complete, high-performance memory controller and PHY solution is future proofed for future memory, and Cadence’s leading design techniques and flexibility enable the introduction of new memory devices into the system and achieve interoperability with excellent system margins.
“SK hynix’s LPDDR5 Turbo mobile DRAM opens up new possibilities beyond smartphones, to AI, machine learning and augmented/virtual reality,” said Sungsoo Ryu, VP of DRAM product planning at SK hynix. “Proving interoperability with Cadence’s memory interface IP is a key step in enabling customers targeting 9600Mbps operation.”
“Cadence LPDDR5X design IP implements the highest performance signal-boosting design techniques,” noted Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “The result is that we can demonstrate wide-open data eyes with a large amount of system margin when operating with SK hynix’s 9600Mbps mobile DRAM.”
The LPDDR5X IP supports Cadence’s Intelligent System Design™ strategy, which enables SoC design excellence with high-performance, design-optimized, best-in-class technology.
