Cadence Design Systems, Inc. announced that the Cadence® 112G-LR SerDes is silicon proven on the HBM3/GLink/CoWoS platform from Global Unichip Corp. (GUC). This milestone in the companies’ ongoing and successful collaboration solidifies Cadence’s leadership in high-performance connectivity IP for the high-bandwidth, high-reliability products that power the most advanced cloud data centers.
GUC’s big-die CoWoS platform represents real-world CPU, GPU, AI, and networking chips by integrating multiple instances of the Cadence 112G-LR SerDes with a 7.2Gbps HBM3 controller and PHY, as well as a GLink-2.5D die-to-die IP in the TSMC N7 process. Cadence collaborated with GUC on the interposer design to meet the strict high-speed signal integrity (SI) and power integrity (PI) requirements of 112G-LR SerDes signaling through silicon (CoWoS-S) and organic (CoWoS-R) interposers. The 112G-LR SerDes has been validated in the GUC CoWoS platform, demonstrating excellent performance and robustness in large-scale AI/HPC/networking chip conditions.
“Our AI/HPC/networking platform on TSMC’s CoWoS® technology meets high-power and high-speed requirements at the system level and demonstrates our industry leadership in delivering complete advanced packaging solutions,” said Igor Elkanovich, CTO at GUC. “Cadence’s robust, production-quality 112G SerDes was instrumental in allowing us to unleash new potential for scalable, multi-die AI, HPC and networking solutions.”
“The successful demonstration of the Cadence 112G-LR SerDes in GUC’s platform using TSMC’s CoWoS technology is a great example of design ecosystem collaboration on 2.5D multi-die packaging solutions,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Cadence’s leading IP solutions together with TSMC’s advanced technologies enable system-level innovations for AI/ML, HPC and networking applications.”
“Our successful collaboration with GUC exemplifies how Cadence is delivering SoC design excellence through our Intelligent System Design strategy,” said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence. “The Cadence 112G-LR/ELR PAM4 SerDes IP portfolio has been widely adopted by customers to enable AI, HPC, networking and 5G SoC designs. This milestone expands our collaboration, enabling GUC to prove their groundbreaking CoWoS platform and solidifying Cadence’s leadership in high-performance connectivity IP offerings.”
The Cadence 112G-LR SerDes incorporates industry-leading analog-to-digital converter (ADC) and digital signal processor (DSP) technology that delivers exceptional long-reach performance with superior margin and optimized power and area. The IP provides multi-rate support including 112/56Gbps in PAM4 mode, as well as 56Gbps and lower data rates in NRZ mode. The IP supports both standard and advanced packaging technologies.
The 112G-LR SerDes IP is part of the broader Cadence IP portfolio and supports the company’s Intelligent System Design Strategy, enabling SoC design excellence.
