Cadence Design Systems, Inc. announced it has expanded its design IP portfolio on TSMC’s 3nm (N3E) process—most notably with the addition of the flagship Cadence® 224G Long-Reach (224G-LR) SerDes PHY IP, which has achieved first-pass silicon success. Other Cadence Design IP on the advanced TSMC N3E process has demonstrated silicon success or taped out, providing mutual customers with a wide range of high-speed interface and memory IP for their most advanced designs. Cadence’s broad portfolio on TSMC’s N3E process delivers industry-leading power, performance and area (PPA) to target the most demanding networking, hyperscale computing, artificial intelligence and machine learning (AI/ML), chiplet, automotive and storage applications.
With the proliferation of bandwidth-hungry, low-latency applications fueled by generative AI and large language models (LLMs), the need for innovative IP solutions that enable efficient and robust high-speed data transmission has become paramount. Addressing this surging demand, the new 224G-LR SerDes PHY IP and other leading Cadence interface IP on the TSMC N3E process usher in a new era of innovation and high-speed connectivity. The 224G-LR SerDes PHY IP features an innovative architecture providing an exceptional combination of speed, reach and power efficiency. Key features include:
- Support for full-duplex 1-225Gbps data rates with excellent LR performance
- Optimized power efficiency configurable for different channel reaches (LR, MR, VSR)
- Built-in intelligence to enhance reliability and system robustness
The 224G-LR PHY IP is part of the Cadence IP portfolio on TSMC’s advanced N3E process, which also includes 112G LR SerDes PHY IP, PCI Express® (PCIe®) 6.0/5.0/4.0/3.0/2.0, 64G/32G Multi-Protocol SerDes, Universal Chiplet Interconnect Express™ (UCIe™), LPDDR5x/5/4x/4, DDR5/4/3 and GDDR7/6 IP. Cadence’s 224G/112G LR SerDes and DDR5 IP have demonstrated first-pass silicon success. The PCIe, 64G/32G Multi-Protocol SerDes, LPDDR5x/5, GDDR7/6 and UCIe IP were successfully taped out in early 2023.
“Cadence’s innovative IP solutions for TSMC’s most advanced N3E process empower our customers to unlock unprecedented levels of performance and power efficiency while benefiting from the leading-edge capabilities of TSMC’s N3E process,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “Our latest collaboration with Cadence on breakthrough IP designs for TSMC’s 3nm technology has the potential to reshape the landscape of hyperscale, AI/ML and 5G/6G infrastructure SoC designs.”
“Our proven interface IP architectures on TSMC’s cutting-edge N3E process have realized significant gains in performance and power efficiency, enabling our mutual customers to harness the benefits of the N3E process while still achieving faster time to market,” said Rishi Chugh, vice president of product marketing for the IP Group at Cadence. “SerDes speeds must quickly move to next-generation nodes to accommodate the increased demand for data bandwidth required by generative AI and other high-speed networking infrastructures. Cadence’s demonstration of 224G-LR silicon offer customers a solid upgrade path to next-generation hyperscale designs. Our close collaboration with TSMC enables us to deliver high-quality IP designed to achieve first-pass silicon success and faster time to market.”
The comprehensive Cadence IP portfolio on the TSMC N3E process supports the Cadence Intelligent System Design™ strategy by enabling advanced-node SoC design excellence.
