Cadence Design Systems, Inc. announced it has collaborated with TSMC to integrate the new Cadence® Virtuoso® Studio into the TSMC N16 mmWave design reference flow and N6RF design reference flow, and added support for the N4PRF design reference flow. With this latest development in Cadence’s and TSMC’s long history of collaboration, joint customers now have access to complete RF design reference flows on the N16, N6, and N4PRF processes for developing optimized, highly reliable, next-generation RFIC designs for use in radar, 5G and WiFi-7 wireless applications for the mobile, automotive, healthcare and aerospace markets. Mutual customers are already using the design reference flows and corresponding TSMC process design kits (PDKs) for RFIC design projects.
The Cadence RFIC solution supports TSMC’s advanced processes and features automation capabilities to help customers spend less time developing and integrating critical RF functionality into their designs. The solution supports all aspects of RF design, including passive device modeling, assisted layout automation, and electromagnetics (EM) simulations.
The flows are supported by the latest version of the Cadence Virtuoso Schematic Editor and can deliver unmatched productivity benefits. Additionally, the flows enable a seamless integration between the Cadence EMX® Planar 3D Solver and Quantus™ Smart View tools for full-circuit extraction without parasitic double counting. The flows are newly enhanced to use purpose mapping for intelligent device scaling when migrating schematics between technology nodes. Purpose mapping allows designers to capture the purpose of devices so that they may be scaled correctly upon process migration, according to their function in the circuit. Furthermore, a new advanced results reviewer provides valuable insight into design sensitivities such as managing corner simulations, and achieving design centering and circuit optimization. The flows also include the Cadence Virtuoso ADE Suite and the integrated Spectre® X Simulator and RF Option.
“Throughout our long-standing and productive collaboration with Cadence, the goal has always been to facilitate customer productivity and innovation by providing design flows that simplify and accelerate the development of advanced ICs,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “By integrating Cadence technologies into our leading-edge RF design flows, customers will be able to meet industry demand for next-generation RFICs that provide low-power, high-performance connectivity to mobile, 5G and WiFi-7 applications.”
“TSMC and Cadence customers are under tremendous pressure to rapidly develop RFIC designs in support of booming demand for 5G and other types of wireless connectivity,” said Tom Beckley, senior vice president and general manager in the Custom IC & PCB Group at Cadence. “Working closely with TSMC, we have updated our RF reference flows to leverage the unparalleled power of our latest release, Virtuoso Studio. We continuously listen to our mutual customers to understand their real-world design requirements, and their feedback has enabled us to tailor our flows so they can deliver leading-edge designs in a timely manner.”
