Synopsys, Inc. announced that its digital and custom/analog design flows are certified for TSMC's N2 process technology, enabling faster delivery of advanced-node SoCs with higher quality. Both flows are seeing strong momentum, with the digital design flow achieving multiple tape-outs and the analog design flow adopted for several design starts. The design flows, powered by the Synopsys.ai™ full-stack AI-driven EDA suite, deliver a significant lift in productivity. Synopsys Foundation and Interface IP in development for the TSMC N2 process will help reduce integration risk and speed time to market for advanced HPC, AI, and mobile SoCs. Additionally, Synopsys AI-driven design technologies, including Synopsys DSO.ai™, are enabled to fast-path the optimization of N2 design to improve the power, performance, and area.
"High quality-of-results and faster time to market for advanced SoC designs are hallmarks of TSMC's and Synopsys' longstanding collaboration," said Dan Kochpatcharin, head of Design Infrastructure Management Division at TSMC. "We work closely with our design ecosystem partners like Synopsys to deliver a full-spectrum of best-in-class solutions for TSMC's most advanced process technologies, providing our mutual customers a clear advantage in meeting the silicon demands of high-performance applications, along with a proven path to rapidly migrate their designs from node to node."
"The Synopsys digital and analog design flows for the TSMC N2 process represent a significant investment by Synopsys across the full EDA stack, helping designers jumpstart their N2 designs, differentiate their SoCs with increasingly better power, performance, and chip density, and accelerate their time to market," said Sanjay Bali, vice president of Strategy and Product Management for the EDA Group at Synopsys. "Our close collaboration with TSMC through every generation of TSMC's process technologies enables us to deliver unmatched EDA and IP solutions that customers need to innovate and strengthen their competitive advantage."
Efficient Reuse of Designs from Node to Node
The Synopsys analog flow enables efficient reuse of designs from node to node on TSMC advanced processes. As part of the certified EDA flows, Synopsys provides interoperable process design kits (iPDKs) and Synopsys IC Validator™ physical verification for full-chip physical signoff.
