Alphawave Semi, a global leader in high-speed connectivity and compute silicon for the world’s technology infrastructure, has announced the successful tape-out of its cutting edge UCIe™ 3D IP on the advanced TSMC SoIC® (SoIC-X) technology in the 3DFabric platform. This achievement builds on Alphawave Semi’s established baseline of leading UCIe™ IP subsystems and presents a significant evolution in the company’s chiplet integration capabilities. By leveraging TSMC’s SoIC-X advanced 3D packaging technology, Alphawave Semi continues to push the boundaries of power, performance efficiency and bandwidth for next generation datacenter, AI, and HPC applications.
The IP supports face-to-face (F2F) configurations and provides a 10x improvement in power efficiency over traditional 2.5D die-to-die interfaces. It also delivers up to a 5x increased signal density.
As AI models grow increasingly complex, traditional scaling methods like Moore’s Law are no longer sufficient to meet the soaring demands of performance, power efficiency, and memory bandwidth. In conventional planar designs, communication between chips occurs at the perimeter or shoreline, which is limited by available edge space. This restricts how much bandwidth, and functionality can be integrated within a single package footprint.
To overcome these limitations, designers are rethinking how memory, I/O, and logic are brought together, and are moving beyond monolithic SoCs toward innovative disaggregated architectures. To break through these barriers, the industry is shifting toward advanced packaging solutions by either expanding silicon horizontally on the package or stacking dies vertically. 3D die stacking offers a compelling path forward for better bandwidth density and power efficiency.
Alphawave Semi’s UCIe-3D 5nm bottom die supports TSVs to supply power and ground to the 3nm top die. The company’s 3DIO portfolio also includes a proprietary design flow and methodology for fast and efficient construction and verification of the 3D stack.
"This successful tape-out represents a significant milestone for Alphawave Semi and our AI platform," said Mohit Gupta, Executive Vice President & General Manager, Alphawave Semi."By combining our high-speed 3D UCIe IP with TSMC's groundbreaking SoIC-X technology, we are directly addressing the memory and bandwidth bottlenecks that limit our customers' next-generation AI and HPC applications. This is a testament to our team's innovation and our commitment to enabling a new class of chiplet-based systems."
“Siemens is pleased to partner with Alphawave Semi to offer both their industry leading 3DIO IP and Siemens’ advanced 3D IC design and verification platforms,” said Juan C. Rey, Senior Vice President and General Manager, Calibre product line, Siemens Digital Industries Software. “This collaboration reflects our shared vision of delivering compelling IP and robust design and verification platforms to our shared customers. Together we are enabling early-stage analysis of critical electrical and thermal parameters that drive the performance, efficiency, and reliability of next-generation 3D IC systems.”
“The partnership we have with our Open Innovation Platform® (OIP) design ecosystem partners like Alphawave Semi is essential for enabling our mutual customers to fully harness TSMC’s industry-leading 3DFabric advanced packaging and 3D stacking technologies in their designs,” said Aveek Sarkar, Director of the Ecosystem and Alliance Management Division at TSMC.“This latest collaboration with Alphawave Semi, advancing UCIe-3D IP on the SoIC-X platform, is a prime example of our drive to enable energy efficiency and higher performance in AI systems, helping our customers push the envelope of product innovation.”
