Cadence Design Systems, Inc. announced it plans to exhibit its system design and verification solutions at the Design and Verification Conference (DVCon) in San Jose, California. The conference is focused on the application of Electronic Design Automation (EDA) standards, languages and methodologies for the design and verification of electronic systems and integrated circuits.
WHEN: March 2 – 5, 2015
WHERE: Hilton Doubletree Hotel, San Jose, CA, Booth 505
WHAT: At booth 505, Cadence is scheduled to showcase the latest tools, methodologies and support customers need for designing and verifying complex silicon, SoCs and systems. Experts will be on hand to discuss topics focused on Verification IP and IC/SoC/system design and verification.
To view the full list of Cadence speaking slots, visit: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=021815_dvcon
