Synopsys, Inc today announced that automotive IC suppliers worldwide are standardizing on its manufacturing test solution to achieve their goals for lower defective parts per million (DPPM), reduced test costs associated with digital and mixed-signal designs, and in-system self-test to ensure functional safety. Semiconductor companies, including Dialog Semiconductor, Intersil Corporation, MegaChips Corporation, Micronas and others, have successfully deployed Synopsys synthesis-based test on their automotive ICs and shipped millions of devices. Adoption continues to grow rapidly as recent innovations in Synopsys' DFTMAX™ and TetraMAX® ATPG, such as pin-limited test compression, advanced fault models and logic built-in self-test, enable automotive IC suppliers to consistently achieve their quality, cost and safety goals on schedule.
Designers of automotive ICs face three key challenging manufacturing test requirements. First, the tests must execute quickly to be cost-effective, even when few test pins are available. To minimize test time and cost for pin-limited and mixed-signal designs, DFTMAX Ultra synthesizes test compression circuitry, utilizing as few as one pair of test pins. Second, ICs for automotive systems must be tested for the highest quality, often requiring less than one DPPM. To achieve this goal, TetraMAX generates test programs that target a wide range of silicon defects using state-of-the-art fault models that incorporate the designs' timing and physical characteristics provided by links across the Synopsys Galaxy™ Design Platform. Finally, safety-critical designs must be able to routinely perform in-system self-test in compliance with the ISO 26262 automotive functional safety standard. To address this requirement, the Synopsys BIST solution synthesizes on-chip circuitry that enables quick in-system testing.
"Synopsys is responding to the needs of a growing number of IC suppliers to ensure their designs are compliant with automotive requirements, including the ISO 26262 standard," said Bijan Kiani, vice president of marketing for Synopsys' Design Group. "Our synthesis-based test solution enables designers to meet these requirements and utilizes value links across the Galaxy Design Platform to maximize designer productivity."
The Synopsys synthesis-based test solution is comprised of DFTMAX Ultra, DFTMAX and TetraMAX for power-aware logic test and physical diagnostics; the DesignWare® STAR Hierarchical System for hierarchical test of IP and cores on an SoC; the DesignWare STAR Memory System® for embedded test, repair and diagnostics; the Yield Explorer® tool for design-centric yield analysis; and the Camelot™ software system for CAD navigation. Synopsys' test solution combines Design Compiler® RTL synthesis with embedded test technology to optimize timing, power, area and congestion for test as well as functional logic, leading to faster time-to-results. The Synopsys test solution delivers tight integration across the Synopsys Galaxy Design Platform, including Design Compiler, IC Compiler™ II place and route, and PrimeTime® timing analysis, to enable faster turnaround time meeting both design and test goals, higher defect coverage and faster yield ramp.
