Cadence Design Systems, Inc. announced that Altair Semiconductor adopted the Cadence® Palladium® XP platform for the verification and validation of its Internet of Things (IoT) system-on-chip (SoC) designs. Using the Palladium XP platform, Altair is able to conduct SoC hardware and software integration and validation three to four months ahead of silicon availability.
Altair utilized the Palladium XP platform to accurately model the register-transfer level (RTL) design running with software and flash memory, enabling them to capture half of all hardware and software bugs in a pre-silicon environment. This reduces the development-cycle turnaround time by 20 percent compared to their previous process. LTE software development for L1, L2 and L3 protocols was completed and verified in the hardware context three to four months before silicon availability.
“As the Internet of Things expands beyond consumer devices to include all types of connected ‘things,’ high-performance, ultra-low-power silicon solutions enabling these connections become key,” said Eli Zyss, vice president of Silicon Design, Altair Semiconductor. “Recently we deployed the Palladium XP platform to address the design and verification challenges of our next-generation IoT and broadband LTE silicon development. This allowed us to shorten the development cycle, improve turnaround-time, and address hardware and software issues pre-silicon.”
The Palladium XP platform, which is part of the Cadence System Development Suite, is a high-performance, special-purpose verification computing platform that unifies best-in-class simulation acceleration and emulation capabilities in a single environment. For more information on the Palladium XP platform, visit www.cadence.com/news/pxp.
