Mentor Graphics Corporation today announced its new Tessent®ScanPro product, which features technology that significantly improves the test pattern volume reduction achievable with the company's Tessent TestKompress® ATPG compression solution. Because the volume of test patterns largely dictates the cost and time to test an integrated circuit (IC), the Tessent ScanPro product helps chip manufacturers to ship their products more quickly and cost effectively.
The key technology in the Tessent ScanPro product, Embedded Deterministic Test (EDT) Test Points, applies local circuit modifications to reduce assignment conflicts that arise during the test pattern generation process. The resulting improvement in pattern generation efficiency translates into significant pattern count reduction. EDT Test Points are effective at reducing patterns generated for all types of fault models, including the advanced Cell-Aware fault model from Mentor®.
"Test times are becoming more problematic as our design sizes continue to grow," said Erez Menahem, Marvel NCD DFT Manager. "Using Mentor's EDT Test Point technology has allowed us to significantly reduce test pattern count, typically by 3x to 4x on several test cases, without any impact on quality."
The Tessent ScanPro product provides automation for inserting the EDT Test Points without affecting design performance or schedule. The analysis and insertion steps fit easily into any DFT flow. Test point locations are carefully chosen as to not impact timing closure. A number of placement constraints can also be controlled by the user.
"Our customers are continuously looking to reduce their test costs as their design sizes grow and quality requirements become more stringent," said Steve Pateras, product marketing director at Mentor Graphics. "Our new EDT Test Point technology in Tessent ScanPro provides a giant leap forward for test compression. Combining the EDT Test Points technology with the Tessent TestKompress solution can result in overall test data volume compression levels in the 200x to 400x range, with compression levels even higher for some designs."
The Tessent ScanPro product also delivers a comprehensive set of advanced scan DFT capabilities. It turns a gate-level netlist into a design that is completely ready for scan testing and pattern compression by generating and adding the most effective scan architecture. It also analyzes the design for possible test limitations, performs test-related design rule checks (DRCs), and automatically corrects errors, if desired. The Tessent ScanPro product also supports the insertion of dedicated and shared wrapper cells for a core-based, hierarchical DFT methodology.
