Cadence Design Systems, Inc. today announced that its digital and signoff tools are now enabled for the current version of the GLOBALFOUNDRIES® 22FDX™ platform reference flow. GLOBALFOUNDRIES has qualified these tools for the 22FDX reference flow to provide customers with the design flexibility of software-controlled body bias to manage power, performance and leakage needed to create next-generation chips for mainstream mobile, Internet of Things (IoT) and consumer applications. In addition, the ARM®Cortex®-A17 processor was used to validate the implementation flow with the Cadence® Innovus™ Implementation System and Genus™ Synthesis Solution.
Cadence collaborated with GLOBALFOUNDRIES on the development of the Process Design Kit (PDK) for the 22FDX platform. The Cadence digital implementation tools support the capability of forward and reverse body bias (FBB/RBB) to optimize the performance/power tradeoffs, implant-aware and continuous diffusion-aware placement, tap insertion and body bias network connectivity according to high voltage rules. The digital implementation tools also support double-patterning aware parasitic extraction (PEX) and design for manufacturing (DFM). Tools in the flow include:
- Genus Synthesis Solution: An RTL synthesis and physical synthesis engine that improves productivity challenges faced by RTL designers, delivering up to 5X faster synthesis turnaround times
- Innovus Implementation System: Advanced physical implementation tool, incorporating a massively parallel architecture that helps designers deliver high-quality SoCs in less time with best-in-class PPA
- Tempus™ Timing Signoff Solution: A complete timing analysis tool that improves signoff timing closure via massively parallel processing and physically aware timing optimization
- Quantus™ QRC Extraction Solution: A parasitic extraction tool that provides faster runtimes for single- and multi-corner extraction and best-in-class accuracy versus foundry golden
In addition, Cadence and GLOBALFOUNDRIES are actively working on the qualification of Voltus™ IC Power Integrity Solution and Physical Verification System (PVS). For more information on the Cadence digital and signoff tools, please visit http://www.cadence.com/products/Pages/all_products.aspx.
"We are collaborating closely with Cadence on enabling their products to help customers realize the benefits of the GLOBALFOUNDRIES 22FDX platform," said Pankaj Mayor, vice president of Business Development at GLOBALFOUNDRIES. "The 22FDX reference flow can enable customers to achieve real-time tradeoff between static power, dynamic power and performance to create innovative products."
"Cadence digital and signoff customers can engage with us now to start realizing the benefits of the GLOBALFOUNDRIES 22FDX platform," said Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence. "Our work with GLOBALFOUNDRIES demonstrates our joint commitment to enabling customers to create innovative, next-generation SoCs that meet advanced technical requirements and aggressive market deadlines."
GLOBALFOUNDRIES plans to deliver a related presentation at ARM TechCon titled, "The Implementation of ARM Cortex-A17 Quad-Core in GLOBALFOUNDRIES 22FDX Technology Using Cadence Innovus Implementation System." The session is scheduled for 2:30 p.m. Pacific Time on Thursday, November 12, 2015, in the Mission City Ballroom M3 at the Santa Clara Convention Center in Santa Clara, Calif.
