Mentor Graphics Corporation today announced availability of verification IP (VIP) for the ARM AMBA 5 AHB on-chip interconnection specification. Available in the Mentor [®] Enterprise Verification Platform™ (EVP), this new VIP simplifies and speeds up the verification process for designers using Questa [®] simulation and Veloce [®] emulation to verify chip designs using the new specification.
As part of the Mentor [®] VIP library, the new VIP provides essential information for verifying designs using the interconnect specification—sequences, test plans, coverage and assertions for the memory types, and security and messaging features.
"The ARM AMBA 5 AHB specification defines on-chip connectivity that is area-efficient, low-latency, and low-power for ARM-based embedded and IoT solutions," said Andy Nightingale, vice president of system IP marketing, systems and software group, ARM. "Mentor Graphics is providing verification IP to simplify development of interconnects for the next generation of ARM-based SoCs to meet the growing demand of the IoT and embedded markets."
The Mentor VIP library provides engineers with standard UVM SystemVerilog (SV) components using a common architecture across all protocols. This allows rapid deployment of multiple protocols within a verification team. Test plans, compliance tests, test sequences and protocol coverage are all included as SV and XML source code, allowing simple re-use, extension and customization. The Mentor VIP components also include a comprehensive set of protocol checks, error injection and debug capabilities.
"The ARM AMBA 5 AHB expands our industry-leading support for AMBA in the Mentor VIP library," said Mark Olen, product manager, Design Verification Technology Division. "Combined with our EZ-VIP productivity package, the Mentor VIP library helps all ARM-based SoC designers and verification engineers identify bugs quickly and reduce overall time to market."
By providing AMBA 5 AHB VIP for use with Questa and Veloce platforms, the EVP helps designers debug block-to-block interactions in simulation, as well as fully verify system-level software running on virtual hardware using high-performance simulation acceleration. Questa simulation brings a complete interactive debug environment, Veloce emulation delivers the highest performance system-level verification throughput, and now both provide complete functional support of the AMBA 5 AHB specification.
Mentor verification IP is a key part of the EVP, which combines Questa [®] advanced verification solutions, Veloce emulation platform, and the Visualizer [™] debug environment into a globally accessible, high-performance, datacenter resource. The Mentor EVP features global resource management that supports project teams around the world, maximizing both user productivity and total verification return on investment.
