Cadence Design Systems and Accusonus have announced that the Accusonus Focus-MDR and Focus-DNR speech enhancement software has been optimized for Cadence Tensilica HiFi audio / voice digital signal processors (DSPs).
Accusonus was able to achieve a 60 percent reduction in computational cost as measured in megacycles per second (MCPS) without any loss of quality. With these optimizations, the Accusonus two-microphone embedded joint de-noise and de-reverberation software products reduced the computational requirement to as little as 4.8 MCPS, making them among the most efficient implementations in the market.
The patented Accusonus algorithms eliminate noise and reverberation while significantly improving speech quality to make conversations intelligible, even when there’s a large distance between the speaker and microphone.
The Tensilica HiFi DSP is the most widely used licensable audio/voice/speech DSP family, with support for over 160 proven audio/voice software packages and over 75 software partners in the Tensilica XtensionsTM partner program, says the company.
“Our products were, from the very beginning, designed to work in tandem with any other technologies running on the HiFi DSPs and to improve their performance in demanding acoustic environments,” said Elias Kokkinis, CTO, Accusonus. “We envision our de-noise and de-reverberation products as essential additional components of any indoor voice processing solution, such as conference systems or IoT devices. By utilizing the flexible architecture of the HiFi DSPs, we have achieved a dramatic improvement in computational performance without any loss of speech quality and our products are now ideal for those cases where computational efficiency is the top priority.”
“The unique and compelling solution offered by Accusonus significantly improves the voice quality of mobile and IoT devices,” added Larry Przywara, group director, Audio/Voice IP Marketing, Cadence. “The dramatic improvement in computational performance provides our customers the advantage of being able to design applications with significantly lower frequency and lower power compared to other architectures.”
