Synopsys, Inc. today announced a broad IP portfolio for TSMC's 16-nanometer FinFET Compact (16FFC) process for reliable integration into cost-sensitive, ultra-low power applications including mobile, Internet of Things (IoT), digital home and automotive. Synopsys DesignWare® IP on the 16FFC process enables designers to accelerate development of SoCs that incorporate logic libraries, embedded memories, embedded test and repair, USB 3.1/3.0/2.0, USB-C 3.1/DisplayPort 1.3, DDR4/3, LPDDR4, PCI Express® 4.0/3.1/2.1, SATA 6G, HDMI 2.0, MIPI M-PHY and D-PHY and data converter IP.
"The 16FFC process reduces SoC power consumption by more than 50 percent (at the same frequency) compared to the 28HPM process and optimizes die area to lower system cost. Synopsys' DesignWare IP portfolio for the TSMC 16FFC process helps our mutual customers achieve their SoC performance, power and area targets," said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. "Synopsys continues to provide proven IP solutions that support TSMC's latest process technologies, helping designers achieve their time-to-market objectives."
"Synopsys' broad portfolio of high-quality IP on the 16FFC process is another significant milestone in our successful history of providing silicon-proven IP in advanced FinFET processes," said John Koeter, vice president of marketing for IP and prototyping at Synopsys. "With a complete, low-power solution including Synopsys PHY IP on the TSMC 16FFC process and digital interface controller IP that supports the IEEE 1801-2009 Unified Power Format, designers can reduce SoC power consumption and extend battery life for smart phones, consumer products and wearables."
The DesignWare Logic Libraries and DDR4/3 PHYs are available now for TSMC 16FFC. DesignWare USB 3.1/3.0/2.0 PHYs, HDMI 2.0 PHYs and MIPI D-PHY design kits are available in March 2016.
