Industry Summary Articles

Cadence Design Systems has announced that its digital, signoff and custom/analog tools have achieved V1.0 Design Rule Manual (DRM) and SPICE certification from TSMC for its 10nm FinFET process. Cadence and TSMC are also continuing to collaborate on the advancement of 7nm technologies and have completed tools certification and the delivery of the latest Process Design Kit (PDK) for mutual customers to initiate early design starts based on the most current version of the DRM and SPICE model.

The Cadence custom/analog, digital and signoff tools have been validated by TSMC on high-performance reference designs, providing customers with innovative methodologies to achieve TSMC's 7nm and 10nm process benefits of higher performance, lower power consumption, and smaller area, Cadence indicated. The certified Cadence tools include the Innovus implementation system, Quantus QRC extraction solution, Tempus timing signoff solution, Voltus IC power integrity solution, Voltus-Fi custom power integrity solution, Virtuoso custom IC advanced-node platform, Spectre simulation platform, physical verification system and litho electrical analyzer.

In addition to the tools certified for TSMC's 10nm process, the Virtuoso Liberate characterization solution and the Virtuoso Variety statistical characterization solution have been validated to deliver accurate Liberty libraries including advanced timing, noise and power models utilizing innovative new methods needed for Liberty Variation Format (LVF) models to enable process variation signoff and electromigration models for ultra-low-power applications. Libraries characterized by these two solutions were used in the 10nm v1.0 STA tool certification.

Cadence and TSMC also validated a custom/mixed-signal design reference flow for the 10nm process. The flow includes the following key capabilities for improving design productivity: Advanced simulation capabilities including variation analysis, EM/IR analysis and self-heating impact; color-aware custom layout including rapid prototyping, automated routing and electrically and LDE-aware design; and Virtuoso layout suite for electrically aware design.

"The certification of our tools enables systems and semiconductor companies to deliver advanced-node designs to market faster for mobile phones, tablets, application processors and high performance computing applications," said Anirudh Devgan, senior VP and GM of the digital & signoff group and the system & verification group at Cadence. "Through our deep collaboration with TSMC, we are actively working with customers on 10nm designs while also advancing the 7nm design process to enable customers to maximize the benefits of these leading-edge process nodes."

"We worked closely with Cadence to certify its set of tools and deliver digital and custom/mixed-signal reference flows that can enable customers to reduce interactions and improve predictability when creating 7nm designs," said Suk Lee, TSMC senior director of design infrastructure marketing division. "This marks the production release of our 10nm technology design support."

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