Industry Summary Articles

Synopsys, Inc. today announced a new suite of embedded memory test and repair features for its DesignWare® STAR Memory System® solution to enable increased test coverage and faster power-on initialization for high-performance automotive, mobile and cloud computing system-on-chips (SoCs). With these new features, designers can achieve a 10x reduction in repair time by eliminating extra cycles and testing only faulty memories. The STAR Memory System includes enhanced hardware and test algorithms to detect and correct a wide variety of dynamic faults prevalent in advanced process technologies, including 7-nm FinFET, both in production test and in the field. In addition, its error correcting code (ECC) compiler mitigates the impact of soft errors by calculating the memory failures in time (FIT) rate, enabling designers to improve the reliability of their systems.

"Moving to a new process node, especially in small geometries, is a big challenge," said Spark Zhang, DFT engineer at HiSilicon. "Using the DesignWare STAR Memory System helped us meet our power, performance, area, and test targets, resulting in first-pass silicon success for our 7-nm FinFET SoC."

"With the increasing amounts of SRAM memory required in today's applications, integrating an efficient test and repair solution can accelerate timing closure and improve system reliability and performance," said John Koeter, vice president of marketing for IP at Synopsys. "The new capabilities in the DesignWare STAR Memory System significantly reduce repair time and improve reliability of SoCs."

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