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Wednesday, November 29, 2017

Cadence Announces Availability of Industry's First PCI Express 5.0 Verification IP

Cadence Design Systems, Inc. today announced the availability of the industry's first Verification IP (VIP) in support of the new PCI Express® (PCIe®) 5.0 architecture. The Cadence® VIP incorporates TripleCheck™ technology, which lets designers quickly and thoroughly complete functional verification of server and storage system-on-chip (SoC) designs based on the PCIe 5.0 specification, providing designers with added confidence that designs can function as originally intended. 

For more information on Cadence VIP with TripleCheck technology for PCIe 5.0, please visit www.cadence.com/go/pcie5vip. 

The differentiated, proven Cadence VIP has supported all recent PCIe standards and has been further optimized for the new 5.0 specification. Adopters of the PCIe 5.0 specification have access to the Cadence TripleCheck technology, which provides a verification plan with measurable objectives linked to the specification features and a comprehensive test suite with thousands of ready-to-run tests to ensure compliance with the specification. This enables designers to save time and deliver higher quality end-products. Additionally, designers have access to the Indago™ Protocol Debug App, which provides protocol-specific interactions between the design, the VIP and the testbench to find the root cause of any design bugs. 

"Our team has successfully utilized the Cadence VIP for previous versions of the PCIe specification, which enabled us to deliver world-leading interconnect solutions for compute and storage infrastructures," said Shlomit Weiss, senior vice president, silicon engineering at Mellanox Technologies. "The Cadence solution for PCIe 5.0 is important to our development of the next generation of our products, to support the need for faster data speeds for high-performance, machine learning, cloud, storage and more applications." 

"By offering the first-to-market VIP for PCIe 5.0, enhanced with TripleCheck technology, we're enabling early adopters to ensure designs are compliant with the specification while achieving the fastest path to IP verification closure," said Michal Siwinski, vice president of product management and operations, System and Verification Group at Cadence. "Our support for the latest protocol demonstrates our commitment to the evolution of the PCIe specification, and customers can start using our solution for PCIe 5.0 immediately." 

The Cadence VIP with TripleCheck technology is part of the Cadence Verification Suite and is optimized for Xcelium™ Parallel Logic Simulation, along with supported third-party simulators. The PCIe 5.0 VIP supports the company's System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of best-in-class core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments. 

To view the original press release, please click here.

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